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DTSTART;TZID=Europe/Stockholm:20260125T090000
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DTSTAMP:20260525T185434
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SUMMARY:FAMES European FD-SOI Design School (EFDS)
DESCRIPTION:The FAMES European FD-SOI Design School (EFDS) is a one-week theoretical and practical training course focused on FD-SOI design. \nThis course is intended for chip designers\, engineers\, Masters and PhD students\, with the purpose of providing the essential scientific and technical foundations for developing integrated circuits using FD-SOI technology. \nObjectives \nAnalog and RF designs can take advantage of FD-SOI by using body-biasing techniques and advanced features. Indeed\, the best and specific practices in analogue design helps the FDSOI technology to set us apart. Similarly\, designing digital circuits in FD-SOI is technically demanding because of the power/performance trade-off\, which is managed thanks to the body-bias control. This implies to be aware of the complete design flow covering high-end simulations as well as back-end features. The aim is to provide designers with the foundations they need to develop chips using the FD-SOI technology. \nAudience \nAny designer working in the field of circuit design (Master\, Engineers\, PhDs) keen to understand the circuit design developed in the framework of the FAMES Pilot Line. \nPrerequisites \nThis course will be designed for chip designers. The objective is to provide a scientific and technical approach of the FD-SOI chip design flow \nSyllabus of courses and hands-on trainings \nTransistor modelling \n\nFDSOI transistor modelling (parasitic effects\, coupling effects\, …)\nIV characterization with FD-SOI (coupling effect)\n\nAnalog and RF design \n\nACM2 and EKV model for FD-SOI\nGm/Id model and circuit design\nParameter extraction\nRF circuit design (LNA)\nPractical trainings\n\nDigital circuit design \n\nFD-SOI digital design flow (from RTL to layout)\nSign-off RTL\nVoltage\, Power and Body bias domain definitions (UPF)\nMiddle-end with constrained synthesis\nStatic timing analysis\nBack-end (floorplanning\, clock tree\, body bias\, routing\, sign-off layout\, …)\nPractical trainings\n\nDesign for Test \n\nDigital test (Fault models\, ATPG\, DfT\, Memory test\, …)\nTest techniques for mixed and analogue circuits\nRF test\nPractical trainings
URL:https://semiconductorsweden.com/event/fames-european-fd-soi-design-school-efds/
LOCATION:Fames\, Grenoble\, France
CATEGORIES:Training
ATTACH;FMTTYPE=image/webp:https://semiconductorsweden.com/wp-content/uploads/2025/11/Screenshot-2025-11-28-084253.webp
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